The term “die” in the field of integrated circuits refers to a small block of semiconducting material, on which a circuit is fabricated. Typically, a die is manufactured as part of a single wafer that includes a plurality of individual dies, in which fabrication techniques (e.g., deposition, removal, patterning, etc.) are utilized to design components and features of each die. The wafer is then cut via a saw-like process to separate each individual die from the larger wafer. The die is connected to a package that allows the packaged die or “chip” to be connected to a circuit board or other suitable device.
In the field of integrated circuits, there is continual pressure to improve performance, whether the integrated circuit is a microprocessor, a solid-state memory device, or some other type of device. For example, with respect to solid-state memory devices, attempts have been made to increase the density of memory devices by creating stacked 3D arrays of memory cell layers in which layer upon layer of memory cells are fabricated on a single substrate. As the number of memory cells increases, the complimentary metal-oxide semiconductor (CMOS) circuitry—a separate semiconductor layer or oftentimes separate semiconductor die fabricated on a different wafer—used to access the memory cells must be scaled (i.e., increased density) in order to provide the desired performance and latency in each generation. In other attempts to increase density, rather than increase the number of memory cell layers in the 3D memory array, a plurality of dies are stacked on top of one another, including memory cell dies, and interposer dies that utilize CMOS circuitry to boost signals. To connect adjacent dies together, the dies are placed adjacent to one another with a layer of metal interconnect located between bonding pads on each die. The metal interconnects are melted to provide bonding between the pads of the respective dies. However, alignment issues and interconnect issues require the bonding pads to remain relatively large to ensure electrical contact between the respective dies. As the density of memory cells on a die increases, additional bonding pads are required in order to provide the desired performance of the memory device, which simply cannot be fit onto the surface area of the memory cell die. Similar issues exist for other types of dies utilized in integrated circuits.
It would therefore be desirable to provide a way of forming die-to-die connections that does not require large bonding pads.